The present invention relates to a semiconductor integrated circuit device and manufacturing method of the device, particularly to a static random access memory (SRAM), on-chip memory mounted on a system LSI, microprocessor, system LSI, and the like.
As a known technique for reducing a gate tunnel leakage current, U.S. Pat. No. 6,307,236 is known. In the known example, when the gate tunnel leakage current is large, a power is cut off with a switch MOS having a thick gate oxide layer and small gate tunnel leakage current, and thereby the leakage current is reduced in a disclosed circuit. Moreover, as a technique for reducing a gate induced drain leakage (GIDL) current, JPA-2000-357962 is known. In the known example, on the assumption that a MOS transistor has a relatively small threshold value, in order to reduce a subthreshold leakage current, a substrate electrode of a P channel type MOS transistor is first controlled to be not less than a power voltage, and the substrate electrode of an N channel type MOS transistor is controlled to be not more than a ground potential. As a result, GIDL is actually generated. To solve the problem, a technique of reducing the power voltage to reduce the GIDL current is disclosed. Moreover, in JP-A-9-135029, as a GIDL current countermeasure, a technique of implanting phosphorus ions in a gate electrode and source/drain region of an N channel MIS transistor is disclosed.
In recent years, with miniaturization of a process, the MOS transistor has had a gate oxide layer thickness of 4 nm or less. However, when the thickness of the gate oxide layer is 4 nm or less, the gate tunnel leakage current increases. When an activating voltage is supplied between gate and source electrodes, the gate tunnel leakage current is 10-12 A/μm2 or more in a typical process.
In an LSI for use in a cellular phone, there is a demand for standby in a low leakage current. Particularly, in a SRAM, it is necessary to retain data with a button battery for one week or more. When the process becomes worst and the oxide layer becomes thin, the gate tunnel leakage current increases and it is disadvantageously impossible to retain the data for one week or more. Moreover, an increase of the GIDL current as the leakage current flowing to a substrate from a drain similarly raises a problem. However, in the conventional known example (U.S. Pat. No. 6,307,236) for reducing the gate tunnel leakage current, the power is cut off with the MOS, and therefore there is a problem that data retained in a SRAM cell, register file, latch circuit, and the like are destroyed. Moreover, in the conventional known example (JP-A-2000-357962) for reducing the GIDL current, when the MOS transistor having a relatively high threshold value, for example, of 0.7 V is used, the subthreshold leakage current is not remarkable. Therefore, even when the substrate electrode of the N channel type MOS transistor is set to a potential not more than the ground potential and the substrate electrode of the P channel type MOS transistor is set to a potential not less than the power voltage, an off leakage current is not reduced, and all the more a junction leak current disadvantageously increases.